I am a senior research engineer at 2012 Labs, Huawei. I received my Ph.D. in Computer Engineering from Northeastern University, where I was advised by Prof. Xiaolin Xu. My focus is on AI infrastructure and OS-side optimization, making AI inference services swift, secure, and scalable.
桃李不言，下自成蹊
Recent roles and research directions.
2025.08 - Now
SRE
Huawei
AI Infrastructure and Memory Management on AI-native-OS.
2020.09 - 2025.05
Research Assistant
Northeastern University
Research on diverse areas, including Vector Symbolic Architectures, Quantum ML, Graph ML, Multi-Party Computation, Hardware Security.
Representative projects and selected publications.
Advanced Binary VSA in machine learning by integrating partial binary neural networks into VSA training. Drastically reduces the vector dimensions required by approximately 99% while maintaining comparable accuracy. Models are only several kilobytes! Prototypes accelerated on FPGA and MCU. Fostered one patent and an NSF award.
Studies robust training for quantum neural networks in the noisy intermediate-scale quantum era. Introduces a noise-aware training strategy that adapts to both standard and fatal error conditions, with a low-complexity search method to identify critical failures during optimization. This approach substantially improves robustness while maintaining competitive performance across diverse error scenarios.
Focuses on graph structural reconstruction with graph autoencoders (GAEs). Introduced a cross-correlation mechanism to enhance GAE representational capabilities addressing limitations in self-correlation models. Proposed GraphCroc, a U-Net-like GAE that ensures robust structural reconstruction through a mirrored encoding-decoding process.
Advances privacy-preserving machine learning through multi-party computation (MPC). Addresses latency issues in MPC with acceleration methods, including FPGA integration and ReLU approximation. Proposed accelerations on FPGA achieved 25% reduced communication and 26x improved energy efficiency compared to existing frameworks.
Proposed a defense framework leveraging placement, routing, and obfuscation to mitigate secret leakage on FPGA components through crosstalk side channels. Reduces leakage by 138 times with minimal latency and area overhead. Won the ACM TODAES Rookie Author of the Year (RAY) Award.
[ArXiv'25] ConQuER: Modular Architectures for Control and Bias Mitigation in IQP Quantum Generative Models.
[ICLRW'25] ProDiF: Protecting Domain-Invariant Features to Secure Pre-Trained Models Against Extraction.
[TODAES'24] Watch Out for the Inherent Vulnerabilities in Developing Multi-tenant Cloud-FPGA: Communication Protocols.
[tinyML'24] Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces.
[ICCAD'23] MirrorNet: A TEE-Friendly Framework for Secure On-device DNN Inference.
[INFOCOM WKSHPS'23] Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers.
[tinyML'23] MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption.
[ICCV'23] VertexSerum: Poisoning Graph Neural Networks for Link Inference.
[ArXiv'23] RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference.
[ICFPT'22] A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure.
[FPGA'22] An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA.
[FCCM'22] NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering.
[NANOARCH'21] Deep Neural Network Security from a Hardware Perspective.
[ISVLSI'21] A Survey of Recent Attacks and Mitigation on FPGA Systems.
NeurIPS(2026-2025), ICML(2026), CVPR(2026), TDSC(2026), PeerJ(2025), JAIR(2024-2025), TIFS(2024), PEVA(2024), TCE(2024), TETC(2023), IEEE-SJ(2021-2023), DAC(2023), HOST(2023), Integration(2022), TOMPECS(2021)
Fundamentals of Digital Design and Computer Organization
Spring 2022, Fall 2020, Fall 2022
Embedded Design: Enabling Robotics
Spring 2021